Intel E7-8891 v2 CM8063601377422 Manual Do Utilizador

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

399

Datasheet Volume Two: Functional Description, February 2014

Intel

®

VT-d registers are all addressed using aligned dword or aligned qword accesses. 

Any combination of bits is allowed within a dword or qword access. The Intel

®

VT-d 

remap engine registers corresponding to the port represented by Device 0, occupy the 
first 4 K of offset starting from the base address defined by VTBAR register.

12:12

RW_L

0x0

disable_trigger_pf_ack2_fix:

Defeature mode to disable fix related to issuing second PF ack for a write 

merged entry. This is only for IRP1.

0: Enable changes
1: Disable changes

Locked by DBGBUSLCK

11:11

RV

-

Reserved:

10:10

RW_L

0x0

lterr_log_dis:

Disable error logging for LT transactions.

9:0

RV

-

Reserved:

VTD0_VERSION

0x0

32

VTD0_CAP

0x8

64

VTD0_EXT_CAP

0x10

64

VTD0_GLBCMD

0x18

32

VTD0_GLBSTS

0x1c

32

VTD0_ROOTENTRYADD

0x20

64

VTD0_CTXCMD

0x28

64

VTD0_FLTSTS

0x34

32

NONISOCH_FLTEVTCTRL

0x38

32

NONISOCH_FLTEVTDATA

0x3c

32

VTD0_FLTEVTADDR

0x40

32

VTD0_FLTEVTUPRADDR

0x44

32

VTD0_PMEN

0x64

32

VTD0_PROT_LOW_MEM_BASE

0x68

32

VTD0_PROT_LOW_MEM_LIMIT

0x6c

32

VTD0_PROT_HIGH_MEM_BASE

0x70

64

VTD0_PROT_HIGH_MEM_LIMIT

0x78

64

VTD0_INV_QUEUE_HEAD

0x80

64

VTD0_INV_QUEUE_TAIL

0x88

64

VTD0_INV_QUEUE_ADD

0x90

64

VTD0_INV_COMP_STATUS

0x9c

32