Intel E7-8891 v2 CM8063601377422 Manual Do Utilizador

486

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

I/OxAPIC DSELS Register 0.

15:15

RO

0x0

pmests:

Not relevant for I/OxAPIC

14:13

RO

0x0

dscl:

Not relevant for I/OxAPIC

12:9

RO

0x0

dsel:

Not relevant for I/OxAPIC

8:8

RO

0x0

pmeen:

Not relevant for I/OxAPIC

7:4

RV

-

Reserved.

3:3

RO

0x1

rstd3hotd0:

Indicates I/OxAPIC does not reset its registers when transitioning from 

D3hot to D0. 

2:2

RV

-

Reserved.

1:0

RW_V

0x0

power_state:

This 2-bit field is used to determine the current power state of the function 

and to set a new power state as well. 
00: D0
01: D1 (not supported by IOAPIC)
10: D2 (not supported by IOAPIC)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not 

change from the existing power state (which is either D0 or D3hot) and nor 

do these bits1:0 change value.
When in D3hot state, I/OxAPIC will 
a) respond to only Type 0 configuration transactions targeted at the device’s 

configuration space, when in D3hot state 
c) will not respond to memory (that is, D3hot state is equivalent to MSE), 

accesses to MBAR region (note: ABAR region access still go through in 

D3hot state, if it enabled)
d) will not generate any MSI writes 

31:29

RV

-

Reserved.

28:28

RWS

0x0

sw2ipc_aer_negedge_msk:

27:27

RWS

0x0

sw2ipc_aer_event_sel:

26:0

RWS

0x0

gttcfg2SIpcIOADels0:

gttcfg2SIpcIOADels0[26:0]