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Intel
J1850
Manual Do Utilizador
Intel J1850 FH8065301455200 Manual Do Utilizador
Códigos do produto
FH8065301455200
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11
Table 123
Summary of HD Audio Memory Mapped I/O Registers—AZLBAR.................. 575
Table 124
Signals ............................................................................................... 700
Table 125
Possible Interrupts Generated From Events/Packets .................................. 702
Table 126
Interrupt Generated for INT[A-D] Interrupts ............................................ 702
Table 127
Summary of PCI Express* PCI Configuration Registers—0/28/0 .................. 705
Table 128
Summary of PCI Express* Lane 0 Electrical Message Bus Registers—0xA6
(Global Offset 200h) ............................................................................. 752
Table 129
Summary of PCI Express* Lane 0 Electrical Message Bus Registers—0xA6
(Global Offset 280h) ............................................................................. 784
Table 130
Summary of PCI Express* Lane 1 Electrical Message Bus Registers—0xA6
(Global Offset 400h) ............................................................................. 801
Table 131
Summary of PCI Express* Lane 1 Electrical Message Bus Registers—0xA6
(Global Offset 480h) ............................................................................. 832
Table 132
Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6
(Global Offset 600h) ............................................................................. 849
Table 133
Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6
(Global Offset 680h) ............................................................................. 880
Table 134
Summary of PCI Express* Lane 3 Electrical Message Bus Registers—0xA6
(Global Offset 800h) ............................................................................. 897
Table 135
Summary of PCI Express* Lane 3 Electrical Message Bus Registers—0xA6
(Global Offset 880h) ............................................................................. 928
Table 136
BBS Configurations............................................................................... 947
Table 137
Summary of PCU iLB LPC Port 80h I/O Registers—.................................... 948
Table 138
PMC Signals......................................................................................... 957
Table 139
Transitions Due to Power Failure ............................................................ 959
Table 140
Transitions Due to Power Button............................................................. 960
Table 141
System Power Planes............................................................................ 962
Table 142
Causes of SMI and SCI.......................................................................... 964
Table 143
INIT# Assertion Causes ........................................................................ 966
Table 144
Summary of PCU iLB PMC Memory Mapped I/O
Registers—PMC_BASE_ADDRESS............................................................ 968
Table 145
Summary of PCI iLB PMC I/O Registers ..................................................1002
Table 146
Summary of PCU iLB PMC I/O Registers—ACPI_BASE_ADDRESS................1005
Table 147
SPI Signals.........................................................................................1024
Table 148
SPI Flash Regions................................................................................1026
Table 149
Region Size Versus Erase Granularity of Flash Components .......................1026
Table 150
Region Access Control..........................................................................1028
Table 151
Hardware Sequencing Commands and Opcode Requirements ....................1032
Table 152
Recommended Pinout for 8-Pin Serial Flash Device ..................................1036
Table 153
Recommended Pinout for 16-Pin Serial Flash Device.................................1036
Table 154
Summary of PCU SPI for Firmware Memory Mapped I/O Registers—
SPI_BASE_ADDRESS ...........................................................................1039
Table 155
UART Signals ......................................................................................1075
Table 156
Baud Rate Examples ............................................................................1076
Table 157
Register Access List .............................................................................1079
Table 158
Summary of PCU iLB UART I/O Registers ................................................1080
Table 159
SMBus Signal Names ...........................................................................1090
Table 160
Enable for PCU_SMB_ALERT# ...............................................................1095
Table 161
Enables for SMBus Host Events .............................................................1095
Table 162
Enables for the Host Notify Command ....................................................1095
Table 163
Host Notify Format ..............................................................................1096
Table 164
Summary of PCU SMBus PCI Configuration Registers—0/31/3 ...................1099
Table 165
Summary of PCU SMBus Memory Mapped I/O
Registers—SMB_Config_MBARL .............................................................1114
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