Intel J1750 FH8065301562600 Manual Do Utilizador
Códigos do produto
FH8065301562600
PCU – iLB – Low Pin Count (LPC) Bridge
1182
Datasheet
24.2.1
Memory Cycle Notes
For cycles below 16M, the LPC Controller will perform standard LPC memory cycles. For
cycles targeting firmware (BIOS/EFI code only), firmware memory cycles are used.
Only 8-bit transfers are performed. If a larger transfer appears, the LPC controller will
break it into multiple 8-bit transfers until the request is satisfied.
cycles targeting firmware (BIOS/EFI code only), firmware memory cycles are used.
Only 8-bit transfers are performed. If a larger transfer appears, the LPC controller will
break it into multiple 8-bit transfers until the request is satisfied.
If the cycle is not claimed by any peripheral (and subsequently aborted), the LPC
Controller will return a value of all 1s to the CPU.
Controller will return a value of all 1s to the CPU.
24.2.2
Trusted Platform Module (TPM) 1.2 Support
The LPC interface supports accessing Trusted Platform Module (TPM) 1.2 devices using
the LPC TPM START encoding. Memory addresses within the range FED00000h to
FED40FFFh will be accepted by the LPC Bridge and sent on LPC as TPM special cycles.
No additional checking of the memory cycle is performed.
the LPC TPM START encoding. Memory addresses within the range FED00000h to
FED40FFFh will be accepted by the LPC Bridge and sent on LPC as TPM special cycles.
No additional checking of the memory cycle is performed.
Note:
This is different to the FED00000h to FED4BFFFh range implemented on some other
Intel components since no Intel
Intel components since no Intel
®
Trusted Execution Technology (Intel
®
TXT)
transactions are supported.
24.2.3
FWH Cycle Notes
If the LPC controller receives any SYNC returned from the device other than short
(0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate
results may occur. A FWH device is not allowed to assert an Error SYNC.
(0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate
results may occur. A FWH device is not allowed to assert an Error SYNC.
BIOS/EFI boot from LPC is not supported when Secure Boot is enabled.
24.2.4
Other Notes
All cycles that are not decoded internally, and are not targeted for LPC (that is,
configuration cycles, IO cycles above 64KB, and memory cycles above 16MB) will be
sent to LPC with ILB_LPC_FRAME# not asserted.
configuration cycles, IO cycles above 64KB, and memory cycles above 16MB) will be
sent to LPC with ILB_LPC_FRAME# not asserted.
24.2.5
POST Code Redirection
Writes to addresses 80h – 8Fh in IO register space will also be passed to the LPC bus.
Note:
Reads of these addresses do not result in any LPC transactions.
24.2.6
Power Management
24.2.6.1
LPCPD# Protocol
Same timings as for PMC_SUS_STAT#. After driving PMC_SUS_STAT# active, the
processor drives ILB_LPC_FRAME# low, and tri-states (or drives low)
ILB_LPC_AD[3:0].
processor drives ILB_LPC_FRAME# low, and tri-states (or drives low)
ILB_LPC_AD[3:0].