Intel J1750 FH8065301562600 Manual Do Utilizador

Intel

Códigos do produto

FH8065301562600

12

Datasheet

Summary of PCU SMBus I/O Registers—SMB_Config_IOBAR..................... 1125

iLB Signals......................................................................................... 1139

NMI Sources ...................................................................................... 1140

Summary of PCU iLB Interrupt Decode and Route Memory Mapped I/O

Registers—ILB_BASE_ADDRESS ........................................................... 1141

LPC Signals........................................................................................ 1181

SERIRQ, Stop Frame Width to Operation Mode Mapping ........................... 1184

SERIRQ Interrupt Mapping ................................................................... 1185

Summary of PCU iLB Low Pin Count (LPC) Bridge PCI Configuration

Registers—0/31/0............................................................................... 1189

Summary of PCU iLB LPC BIOS Control Memory Mapped I/O Registers—

RCRB_BASE_ADDRESS........................................................................ 1209

RTC Signals ....................................................................................... 1210

Register Bits Reset by ILB_RTC_RST# Assertion ..................................... 1213

I/O Registers Alias Locations ................................................................ 1214

RTC Indexed Registers ........................................................................ 1214

Summary of PCU iLB Real Time Clock (RTC) I/O Registers........................ 1216

8254 Signals ...................................................................................... 1218

Counter Operating Modes .................................................................... 1220

Register Aliases .................................................................................. 1222

Summary of PCU iLB 8254 Timers I/O Registers...................................... 1223

8254 Interrupt Mapping....................................................................... 1231

Summary of PCU iLB High Performance Event Timer (HPET) Memory

Mapped I/O Registers.......................................................................... 1232

GPIO Signals...................................................................................... 1241

Summary of PCU iLB I/O APIC Memory Mapped I/O Registers ................... 1251

Interrupt Controller Connections ........................................................... 1253

Interrupt Status Registers.................................................................... 1254

Content of Interrupt Vector Byte........................................................... 1255

I/O Registers Alias Locations ................................................................ 1260

Summary of PCU iLB 8259 Interrupt Controller (PIC) I/O Registers............ 1262