Intel J1750 FH8065301562600 Manual Do Utilizador

Datasheet

319

9:8

0h

RW

cri_data_dynclkgate_mode_1_0: Controls the dynamic clock gating behavior in the 

data lane. 00 - susclk gating and laneclkreq disabled (Forced to configured value). In 

this mode the susclk will not be gated under any circumstances and the laneclkreq sent 

out of the lane will be forced to a programmed value (can be forced high or low) 01 - 

susclk gating disabled, laneclkreq enabled . In this mode the susclk will not be gated 

under any circumstances. The laneclkreq sent out of the data lane will toggle based on 

whether the lane power state, susclk need and the previous lane's laneclkreq signal. 10 

- susclk gating enabled, laneclkreq disabled (forced to configured value) - In this mode 

the susclk will be gated during P2/Slumber when there are no requests to change the 

TX common mode. The laneclkreq sent out of the lane will be forced to a programmed 

value (can be forced high or low) 11 - susclk gating and laneclkreq enabled - In this 

mode the susclk will be gated during P2/Slumber when there are no requests to change 

the TX common mode. The laneclkreq sent out of the data lane will toggle based on the 

lane power state, susclk need and the previous lane's laneclkreq signal.

7

0h

RW

cri_eios_waittime_ovren: EIOS Wait Time Override Enable for Rx Turn OFF 0: 

hardware value for EIOS wait timer is selected. 1: selects cri_eios_waittime[6:0]

6:0

20h

RW

cri_eios_waittime_6_0: EIOS Wait Time for Rx Turn OFF Represents override value 

timer in PCS that comes into play during EIOS based turn off Rx (Rx L0s) 0000000 - 

Timer is bypassed 0000001 - 1 PLL link clock period delay (2ns) 0000010 - 2 PLL link 

clock period delay (4ns) ... 0100000 - 32 PLL link clock periods delay (64ns) - default