Intel J1750 FH8065301562600 Manual Do Utilizador
Códigos do produto
FH8065301562600
Datasheet
59
Integrated Clock
§
Platform Clocks
PMC_PLT_CLK [5:0]
19.2/25 MHz
Platform clocks. For example:
PLT_CLK [2:0] - Camera
PLT_CLK [3] - Audio Codec
PLT_CLK [2:0] - Camera
PLT_CLK [3] - Audio Codec
NOTE: Intel recommends 25 MHz. 19.2
MHz is not validated.
SIO SPI
SIO_SPI_CLK
15 MHz
SPI clock output
I
2
C
SIO_I2C[6:0]_CLK
100 kHz,
400 kHz,
1 MHz,
3.4 MHz
400 kHz,
1 MHz,
3.4 MHz
I
2
C clocks
NOTE: In I
2
C Controller the parameter
called IC_CAP_LOADING can be
set to 400pf/100pf. As per
specification 3.4MHz is supported
in 100pf loading while 1.7MHz is
the maximum frequency at 400pf
load.
SMBus
PCU_SMB_CLK
10-100 kHz
Drives SMBus device
Table 39. Processor Clock Outputs (Sheet 2 of 2)
Clock Domain
Signal Name
Frequency
Usage/Description