Intel Xeon 5130 2.0GHz 124716 Ficha De Dados
Códigos do produto
124716
Electrical Specifications
34
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
Figure 2-6. Dual-Core Intel® Xeon® Processor LV 5148/5138/5128 V
CC
Static and
Transient Tolerance Load Lines
Notes:
1.
The V
CC_MIN
and V
CC_MAX
loadlines represent static and transient limits. Please see
for VCC
overshoot specifications.
2.
Refer to
for processor VID information.
3.
Refer to
for V
CC
Static and Transient Tolerance
4.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
value.
3.
V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4.
V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the
signal quality specifications.
5.
This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
Measured at 0.31*V
TT
. R
ON
(min) = 0.225*R
TT
. R
ON
(typ) = 0.250*R
TT
. R
ON
(max) = 0.275*R
TT
.
6.
GTLREF should be generated from V
TT
with a 1% tolerance resistor divider. The V
TT
referred to in these
specifications is the instantaneous V
TT
.
7.
Specified when on-die R
TT
and R
ON
are turned off. V
IN
between 0 and V
TT
.
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
0
10
20
30
40
Icc [A]
Vc
c
[
V
]
Vcc
Maximum
Maximum
Vcc
Minimum
Minimum
Vcc
Typical
Typical
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
0
10
20
30
40
Icc [A]
Vc
c
[
V
]
Vcc
Maximum
Maximum
Vcc
Minimum
Minimum
Vcc
Typical
Typical
Table 2-15. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
V
IL
Input Low Voltage
-0.10
0
GTLREF-0.10
V
2,4,6
V
IH
Input High Voltage
GTLREF+0.10
V
TT
V
TT
+0.10
V
3,6
V
OH
Output High Voltage
V
TT
- 0.10
N/A
V
TT
V
4,6
R
ON
Buffer On Resistance
10.00
11.50
13.00
Ω
5
I
LI
Input Leakage Current
N/A
N/A
± 100
μA
7
Table 2-16. CMOS Signal Group and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
V
IL
Input Low Voltage
-0.10
0.00
0.3*V
TT
V
2,3
V
IH
Input High Voltage
0.7*V
TT
V
TT
V
TT
+0.1
V
2
V
OL
Output Low Voltage
-0.10
0
0.1*V
TT
V
2