Intel MFS5000SI MFS5000SIB Manual Do Utilizador
Códigos do produto
MFS5000SIB
Intel® Compute Module MFS5000SI TPS
2BFunctional Architecture
3.1 Intel
®
5000P Memory Controller Hub (MCH)
This section describes the general functionality of the memory controller hub as it is implemented on this
server board.
server board.
The MCH is a single 1432-pin FCBGA package, which includes the following core platform functions:
System Bus Interface for the processor subsystem
Memory
Memory
Controller
PCI Express* Ports, including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBus
FBD Thermal Management
SMBus
Interface
Additional information about MCH functionality can be obtained from the Intel
®
5000 Series Chipsets
Server Board Family Datasheet
and the Intel
®
5000P Memory Controller Hub External Design
Specification.
3.1.1
System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front-side bus interfaces
that connect to the Dual-Core and Quad-Core Intel
that connect to the Dual-Core and Quad-Core Intel
®
Xeon
®
processors 5000 sequence. Each front-side
bus on the MCH uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333-MHz data bus is capable of
transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of
addressing up to 64 GB of memory. The MCH is the priority agent for both front-side bus interfaces, and
is optimized for one processor on each bus.
transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of
addressing up to 64 GB of memory. The MCH is the priority agent for both front-side bus interfaces, and
is optimized for one processor on each bus.
3.1.2
Processor Support
The Intel
®
Compute Module MFS5000SI supports one or two Dual-Core Intel
®
Xeon
®
processors 5100
sequence or Quad-Core Intel
®
Xeon
®
processors 5300 and 5400 sequence with system bus speeds of
1066 MHz and 1333 MHz. Previous generations of the Intel
®
Xeon
®
processor are not supported in the
Intel
®
Compute Module MFS5000SI. To see a list of the latest processors that have been validated on
this product, refer to
and select
the Supported Processors List.
3.1.2.1
Processor Population Rules
When two processors are installed, both must be of identical revision, core voltage, and bus/core speed.
Mixed processor steppings is supported in N and N-1 configurations only. When only one processor is
installed, it must be in the socket labeled CPU1. The other socket must be empty.
Mixed processor steppings is supported in N and N-1 configurations only. When only one processor is
installed, it must be in the socket labeled CPU1. The other socket must be empty.
The board is designed to provide up to 115 A of current per processor. Processors with higher current
requirements are not supported.
requirements are not supported.
When using a single processor configuration, a terminator is not required in the second processor socket.
Revision 1.4
7
Intel order number: E15154-007