Intel Pentium 4 641 HH80552PG0882M Manual Do Utilizador
Códigos do produto
HH80552PG0882M
20
Datasheet
Electrical Specifications
NOTES:
1. Refer to
for signal descriptions.
2. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
signals are no connects.
3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration
options. See
for details.
.
2.7
GTL+ Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input
buffers. All of these signals follow the same DC requirements as GTL+ signals, however the
outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These
signals do not have setup or hold time specifications in relation to BCLK[1:0].
buffers. All of these signals follow the same DC requirements as GTL+ signals, however the
outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These
signals do not have setup or hold time specifications in relation to BCLK[1:0].
All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six
BCLKs in order for the processor to recognize the proper signal state. See
BCLKs in order for the processor to recognize the proper signal state. See
additional timing requirements for entering and leaving the low power states.
Table 2-4. Signal Characteristics
Signals with R
TT
Signals with no R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT
BNR#, BOOTSELECT
1
, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
NOTES:
1.
The BOOTSELECT signal has a 500-5000
Ω pull-up to V
TT
rather than on-die termination.
A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],
COMP[5:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],
THERMDA, THERMDC, THERMTRIP#, VID[5:0],
VTTPWRGD, GTLREF, TCK, TDI, TRST#, TMS
COMP[5:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],
THERMDA, THERMDC, THERMTRIP#, VID[5:0],
VTTPWRGD, GTLREF, TCK, TDI, TRST#, TMS
Open Drain Signals
2
2.
Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/PBE#,
IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0],
MSID[1:0]
IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0],
MSID[1:0]
Table 2-5. Signal Reference Voltages
GTLREF
V
TT
/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,
BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
RSP#, TRDY#
BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
RSP#, TRDY#
BOOTSELECT, VTTPWRGD, A20M#,
IGNNE#, INIT#, PWRGOOD
IGNNE#, INIT#, PWRGOOD
STPCLK#, TCK
1
, TDI
NOTES:
1.
These signals also have hysteresis added to the reference voltage. See
for more information.