Microchip Technology IC MCU FLASH 4K PIC16LF88-I/P DIP-18 MCP PIC16LF88-I/P Guia De Informação
Códigos do produto
PIC16LF88-I/P
© 2007 Microchip Technology Inc.
DS80132F-page 1
SSP MODULE
The PIC
®
microcontrollers you have received all exhibit
anomalous behavior in their Synchronous Serial Port
(SSP) modules, as described in this document. They
otherwise conform functionally to the descriptions pro-
vided in their respective Device Data Sheets and Ref-
erence Manuals, as amended by silicon release errata
for particular devices.
(SSP) modules, as described in this document. They
otherwise conform functionally to the descriptions pro-
vided in their respective Device Data Sheets and Ref-
erence Manuals, as amended by silicon release errata
for particular devices.
Users are encouraged to review the latest device data
sheets and errata available for additional information
concerning an individual device. These documents
may be obtained directly from the Microchip corporate
web site, at www.microchip.com.
sheets and errata available for additional information
concerning an individual device. These documents
may be obtained directly from the Microchip corporate
web site, at www.microchip.com.
Silicon Errata
These issues are expected to be resolved in future
silicon revisions of the designated parts.
silicon revisions of the designated parts.
The silicon issues identified in this “Silicon Errata” section
affect all silicon revisions of the following devices:
affect all silicon revisions of the following devices:
1.
Module: I
2
C™ (Slave Mode)
In its current implementation, the module may fail
to correctly recognize certain Repeated Start
conditions. For this discussion, a Repeated Start is
defined as a Start condition presented to the bus
after an initial valid Start condition has been recog-
nized and the Start status bit (SSPSTAT<3>) has
been set and before a valid Stop condition is
received.
to correctly recognize certain Repeated Start
conditions. For this discussion, a Repeated Start is
defined as a Start condition presented to the bus
after an initial valid Start condition has been recog-
nized and the Start status bit (SSPSTAT<3>) has
been set and before a valid Stop condition is
received.
If a Repeated Start is not recognized, a loss of
synchronization between the Master and Slave
may occur; the condition may continue until the
module is reset. A NACK condition, generated by
the Slave for any reason, will not reset the module.
synchronization between the Master and Slave
may occur; the condition may continue until the
module is reset. A NACK condition, generated by
the Slave for any reason, will not reset the module.
This failure has been observed only under two
circumstances:
circumstances:
• A Repeated Start occurs within the frame of a
data or address byte. The unexpected Start
condition may be erroneously interpreted as a
data bit, provided that the required conditions
for setup and hold times are met.
condition may be erroneously interpreted as a
data bit, provided that the required conditions
for setup and hold times are met.
• A Repeated Start condition occurs between two
back-to-back slave address matches in the
same Slave, with the R/W bit set to Read (= 1)
in both cases. (This circumstance is regarded
as being unlikely in normal operation.)
same Slave, with the R/W bit set to Read (= 1)
in both cases. (This circumstance is regarded
as being unlikely in normal operation.)
Work around
A time-out routine should be used to monitor the
module’s operation. The timer is enabled upon the
receipt of a valid Start condition; if a time-out
occurs, the module is reset. The length of the time-
out period will vary from application to application
and will need to be determined by the user.
module’s operation. The timer is enabled upon the
receipt of a valid Start condition; if a time-out
occurs, the module is reset. The length of the time-
out period will vary from application to application
and will need to be determined by the user.
Two methods are suggested to reset the module:
1. Change the mode of the module to something
other than the desired mode by changing the set-
tings of bits, SSPM3:SSPM0 (SSPCON<3:0>);
then, change the bits back to the desired
configuration.
tings of bits, SSPM3:SSPM0 (SSPCON<3:0>);
then, change the bits back to the desired
configuration.
2. Disable the module by clearing the SSPEN bit
(SSPCON<5>); then, re-enable the module by
setting the bit.
setting the bit.
Other methods may be available.
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SSP Module Silicon/Data Sheet Errata