Cypress Semiconductor CY3280-MBR3 Ficha De Dados
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Document Number: 001-85330 Rev. *G
Page 10 of 37
CY8CMBR3102 (2 Sensing Inputs)
CY8CMBR3002 (2 Sensing Inputs)
Table 5. Pin Diagram and Definitions - CY8CMBR3102
8-SOIC
Pin # Pin Name
Type
Description
If unused
Default
Configuration
Pin Diagram
1
I2C SCL
DIO
I2C clock
Leave open
I2C SCL
2
CMOD
–
External modulator capacitor.
Connect 2.2 nF/5 V/X7R or NPO
capacitor
NA
CMOD
3
VCC
Power
Internal regulator output. Connect a
0.1-µF decoupling capacitor if VDD
> 1.8 V. If VDD is 1.71 V to 1.89 V,
short this pin to VDD.
NA
VCC
4
VDD
Power
Power
NA
VDD
5
VSS
Power
Ground
NA
VSS
6
CS1/PS1/
GPO0/SH
I/DO/O
CapSense button / proximity sensor/
GPO/ shield electrode (SPO0 in the
Ground/Ground/
Leave open/leave
Open
GPO0
7
CS0/PS0
–
CapSense button / proximity sensor,
controls GPO0
Leave open/Leave
open
CS0
8
I2C SDA
DIO
I2C data
Leave open
I2C SDA
Legend: I = Analog Input, O = Analog Output, DIO = Digital Input/Output, CS = CapSense Button, PS = Proximity Sensor,
SH = Shield Electrode, GPO = General Purpose Output, SPO = Special Purpose Output.
Table 6. Pin Diagram and Definitions - CY8CMBR3002
8-SOIC
Pin #
Pin Name
Type
Description
If unused
Pin Diagram
1
GPO1
DO
GPO
Leave open
2
CMOD
I/O
External modulator capacitor.
Connect 2.2 nF/5 V/X7R or NPO
capacitor
NA
3
VCC
Power
Internal regulator output. Connect
a 0.1-µF decoupling capacitor if
VDD > 1.8 V. If VDD is 1.71 V to
1.89 V, short this pin to VDD.
NA
4
VDD
Power
Power
NA
5
VSS
Power
Ground
NA
6
CS1
–
CapSense button, controls GPO1
Ground
7
CS0
–
CapSense button, controls GPO0
Leave open
8
GPO0
DO
GPO
Leave open
Legend: I = Analog Input, DO = Digital Output, CS = CapSense Button, GPO = General Purpose Output
SOIC
1
2
3
4
2
3
4
8
7
6
5
7
6
5
Vdd
P0[4], A, I
P0[2], A, I
P1[0], I2C SDA
P0[2], A, I
P1[0], I2C SDA
, I, P0[5]
, I, P0[3]
, I, P0[3]
CL, P1[1]
Vss
I2C SCL
I2C SDA
CMOD
VCC
VDD
CS0/PS0
CS1/PS1/GPO0/SH
VSS
SOIC
1
2
3
4
2
3
4
8
7
6
5
7
6
5
Vdd
P0[4], A, I
P0[2], A, I
P1[0], I2C
P0[2], A, I
P1[0], I2C
, I, P0[5]
, I, P0[3]
, I, P0[3]
CL, P1[1]
Vss
GPO1
GPO0
CMOD
VCC
VDD
CS0
CS1
VSS