Microchip Technology IC MCU FLASH PIC16F676-I/ST TSSOP-14 MCP PIC16F676-I/ST Ficha De Dados
Códigos do produto
PIC16F676-I/ST
PIC16F630/676
DS40039F-page 44
2010 Microchip Technology Inc.
REGISTER 6-2:
VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
6.9
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CMIE bit (PIE1<3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CMIE bit (PIE1<3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON. This will end the
interrupt in the following manner:
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
TABLE 6-2:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
—
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
VREN: CV
REF
Enable bit
1 = CV
REF
circuit powered on
0 = CV
REF
circuit powered down, no I
DD
drain
bit 6
Unimplemented: Read as ‘0’
bit 5
VRR: CV
REF
Range Selection bit
1
= Low range
0
= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR3:VR0: CV
REF
value selection bits 0
VR [3:0] 15
When VRR = 1: CV
REF
= (VR3:VR0 / 24) * V
DD
When VRR = 0: CV
REF
= V
DD
/4 + (VR3:VR0 / 32) * V
DD
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000 0000 000u
0Ch
PIR1
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF 00-- 0--0 00-- 0--0
19h
CMCON
—
COUT
—
CINV
CIS
CM2
CM1
CM0
-0-0 0000 -0-0 0000
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE 00-- 0--0 00-- 0--0
85h
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
99h
VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 0-0- 0000
Legend:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.