Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Ficha De Dados
Códigos do produto
PIC18F65K22-I/PT
PIC18F87K22 FAMILY
DS39960D-page 420
2009-2011 Microchip Technology Inc.
28.2.1
CONTROL REGISTER
shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT Enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
bit that allows software to override the WDT Enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
TABLE 28-2:
SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 28-16: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
U-0
R-x
R/W-0
U-0
R/W-0
R/W-0
R/W-0
REGSLP
—
ULPLVL
SRETEN
)
—
ULPEN
ULPSINK
SWDTEN
(
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP:
Regulator Voltage Sleep Enable bit
1
= Regulator goes into Low-Power mode when device’s Sleep mode is enabled
0
= Regulator stays in normal Operation mode when device’s Sleep mode is activated
bit 6
Unimplemented
: Read as ‘0’
bit 5
ULPLVL:
Ultra Low-Power Wake-up Output bit
Not valid unless ULPEN = 1.
1
= Voltage on RA0 pin > ~ 0.5V
0
= Voltage on RA0 pin < ~ 0.5V.
bit 4
SRETEN:
Regulator Voltage Sleep Disable bit
1
= If RETEN (CONFIG1L<0>) = 0 and the regulator is enabled, the device goes into Ultra Low-Power
mode in Sleep
0
= The regulator is on when the device’s Sleep mode is enabled and the Low-Power mode is
controlled by REGSLP
bit 3
Unimplemented
: Read as ‘0’
bit 2
ULPEN:
Ultra Low-Power Wake-up Module Enable bit
1
= Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates the comparator output
0
= Ultra Low-Power Wake-up module is disabled
bit 1
ULPSINK:
Ultra Low-Power Wake-up Current Sink Enable bit
Not valid unless ULPEN = 1.
1
= Ultra Low-Power Wake-up current sink is enabled
0
= Ultra Low-Power Wake-up current sink is disabled
bit 0
SWDTEN:
Software Controlled Watchdog Timer Enable bit
(
)
1
= Watchdog Timer is on
0
= Watchdog Timer is off
Note 1:
This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled.
2:
This bit is available only when ENVREG = 1 and RETEN = 0.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
WDTCON
REGSLP
—
ULPLVL
SRETEN
—
ULPEN
ULPSINK
SWDTEN
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.