Texas Instruments TLK1221EVM Evaluation Module TLK1221EVM TLK1221EVM Ficha De Dados
Códigos do produto
TLK1221EVM
www.ti.com
PARALLEL BIT
NUMBERS
PARALLEL BIT
NUMBERS
PIN TYPE OF
ROW
8
9
GND
RD [9 :0]
TD [9 :0]
GND
TD [9 :0]
VDD
2
3
7
6
5
4
8
9
2
3
7
6
5
4
0
1
0
1
JMP6
8
9
2
3
7
6
5
4
8
9
2
3
7
6
5
4
0
1
0
1
GND
RD [9 :0]
GND
TD [9 :0]
VDD
PARALLEL
LOOPBACK
JMP6
TLK1221 EVM Board Configuration
The power planes are split three ways to provide power to different parts of the board. This prevents
coupling of switching noise between the analog and digital sections of the TLK1221, and provides voltage
isolation for power consumption testing. The VDD, VDDA, and VDDPLL connectors require a nominal
2.5V and are joined together by removable jumpers on headers JMP9 and JMP10 that are installed in the
default configuration. Thus only the VDD connection is necessary to energize the TLK1221 device in the
default configuration. In all sections of the board, the ground planes are common and each ground plane
is tied together at every component ground connection. See the Schematics and Board Layouts for
detailed schematic and layout information.
coupling of switching noise between the analog and digital sections of the TLK1221, and provides voltage
isolation for power consumption testing. The VDD, VDDA, and VDDPLL connectors require a nominal
2.5V and are joined together by removable jumpers on headers JMP9 and JMP10 that are installed in the
default configuration. Thus only the VDD connection is necessary to energize the TLK1221 device in the
default configuration. In all sections of the board, the ground planes are common and each ground plane
is tied together at every component ground connection. See the Schematics and Board Layouts for
detailed schematic and layout information.
The board is normally delivered in a default configuration that only requires power as well as an external
clock and data inputs. The TLK1221 is shipped with jumpers for default operation.
clock and data inputs. The TLK1221 is shipped with jumpers for default operation.
shows the
default configuration for sending data.
The parallel signals on the TLK1221 EVM have been routed to a 0.1 inch header block that is configured
as in
as in
. All RD pins (RD[9:0]) on the header block (JMP6), as well as all TD pins (TD[9:0]) on the
header block (JMP6) have matched trace lengths to themselves
±
1MIL. Due to routing constraints RXD
and TXD trace lengths are not matched to each other, but only to themselves.
Figure 1. Parallel Signal Header Block
Parallel loop back, shown in
, can be easily implemented by placing jumpers on the RD/TD pins of
the header. For example, placing a jumper on pins 2 and 3 of JMP6 will loop back TD[0] to RD[0].
Figure 2. Parallel Signal Header Block
Additional GND and VDD pins have been added into the header block for several reasons. The GND pins
SLLU100 – September 2007
TLK1221 Ethernet Transceiver Evaluation Module (EVM)
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