takeMS PC 133 128MB BD128TEC200 Manual Do Utilizador

BD256TEC304.fm Rev. A 04/2005

CLK

Input

System Clock: Active on the positive going edge to sample all inputs.

CS#

Input

Chip Select: Disables or enables device operation by masking or enabling all inputs, except CLK, 
CKE, and DQM.

CKE

Input

Clock Enable: Masks system clock to freeze operation from the next clock cycle. CKE should be 
enabled at least one cycle prior to a new command. Disable input buffers for power-down in 
Standby. CKE should be enabled one CLK+tss prior to valid command.

A0 ~ A12

Input

Address: Row/column addresses are multiplexed on the same pins. Row address: RA0 ~ RA12; 
column address: CA0 ~ CA10.

BA0 ~ BA1

Input

Bank Select Address: Selects bank to be activated during Row Address Latch Time. Selects 
bank to be activated during read/write Column Address Latch Time.

RAS#

Input

Row Address Strobe: Latches the row address on the positive going edge of the CLK with RAS 
low.

CAS#

Input

Column Address Strobe: Latches the column address on the positive going edge of the CLK with 
CAS low. Enables column access.

WE#

Input

Write Enable: Enables write operation and row precharge. Latches data, starting from CAS, WE 
active.

DQM0 ~ DQM7

Input

Makes data output Hi-Z, Tshz after the clock and masks the output. Blocks data input when DQM 
is active (Byte masking).

DQ0 ~ DQ63

Input/Output Data inputs and outputs are masked on the same pins.

V

DD

 / V

SS

Supply

Power Supply/Ground: Power and ground for the input buffers and core logic.

NC

-

Do not connect.

CB0 ~ CB7

Input/Output Used on ECC modules.