Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Ficha De Dados
Códigos do produto
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.3.5
C28x Serial Communications Interface
This device has one SCI peripheral. SCI is a two-wire asynchronous serial port, commonly known as a
UART. The SCI module supports digital communications between the CPU and other asynchronous
peripherals that use the standard non-return-to-zero (NRZ) format
UART. The SCI module supports digital communications between the CPU and other asynchronous
peripherals that use the standard non-return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register.
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register.
Features of the SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
–
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
NOTE: Both pins can be used as GPIO if not used for SCI.
–
Baud rate programmable to 64K different rates
•
Data-word format
–
–
One start bit
–
Data-word length programmable from one to eight bits
–
Optional even/odd/no parity bit
–
One or two stop bits
•
Four error-detection flags: parity, overrun, framing, and break detection
•
Two wake-up multiprocessor modes: idle-line and address bit
•
Half- or full-duplex operation
•
Double-buffered receive and transmit functions
•
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
•
NRZ format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper
byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect.
When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper
byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect.
•
Auto baud-detect hardware logic
•
16-level transmit and receive FIFO
shows the C28x SCI peripheral.
Copyright © 2012–2014, Texas Instruments Incorporated
Peripheral Information and Timings
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