Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Ficha De Dados
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DK-TM4C129X
Register 81: Ethernet PHY Configuration 1 - MR9 (EPHYCFG1), address 0x009
This register configuration for the Ethernet PHY. These configuration values are programmed by
the system processor after a POR. The
the system processor after a POR. The
DONE
bit in the EPHYCFG1 register is set when configuration
is complete. This register is used when the user requires a configuration different from what is
provided in the EMACPC register.
provided in the EMACPC register.
Ethernet PHY Configuration 1 - MR9 (EPHYCFG1)
Base n/a
Address 0x009
Type RW, reset 0x0000
Address 0x009
Type RW, reset 0x0000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
FRXDVDET
FANSEL
FASTANEN
RAMDIX
FAMDIX
LLR
TDRAR
reserved
DONE
RO
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
WO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Configuration Done
This bit reads as a zero. The application must write a one to this bit to
terminate the PHYHOLD mode set in the EMACPC register and wake
up the EPHY.
terminate the PHYHOLD mode set in the EMACPC register and wake
up the EPHY.
Description
Value
Configuration process is not complete.
0
Configuration process is complete, and the PHY can continue
and complete its internal reset sequence.
and complete its internal reset sequence.
1
0
WO
DONE
15
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
14:9
TDR Auto-Run at Link Down
Description
Value
Disable automatic execution of TDR.
0
Enable execution of TDR procedure after link down event.
1
0
RW
TDRAR
8
Link Loss Recovery
Description
Value
Normal Link Loss operation
Link status goes down approximately 250 µs from signal loss.
0
Enable Link Loss Recovery mechanism
This mode allows recovery from short interference and continues
to hold the link up for a period of an additional few µs until the
short interference is gone and the signal is OK.
to hold the link up for a period of an additional few µs until the
short interference is gone and the signal is OK.
1
0
RW
LLR
7
December 13, 2013
1800
Texas Instruments-Advance Information
Ethernet Controller