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© 2007-2012 Microchip Technology Inc.

DS70292G-page 91

dsPIC33FJ32GP302/304,  dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices implement a
total of 30 registers for the interrupt controller: 
• INTCON1 
• INTCON2 
• IFSx
• IECx
• IPCx 
• INTTREG

7.3.1

INTCON1 AND INTCON2

Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable bit (NSTDIS) as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.

7.3.2

IFS

X

The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.

7.3.3

IEC

X

The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.

7.3.4

IPC

X

The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels. 

7.3.5

INTTREG

The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level bits (ILR<3:0>) in
the INTTREG register. The new interrupt priority level
is the priority of the pending interrupt. 
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in 

. For example, the INT0 (External

Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>). 

7.3.6

STATUS/CONTROL REGISTERS

Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS register, SR, contains the 

IPL<2:0> bits (SR<7:5>). These bits indicate the 
current CPU interrupt priority level. The user 
software can change the current CPU priority 
level by writing to the IPL bits. 

• The CORCON register contains the IPL3 bit 

which, together with IPL<2:0>, also indicates the 
current CPU priority level. IPL3 is a read-only bit 
so that trap events cannot be masked by the user 
software.

All Interrupt registers are described in 

through 

Many useful resources related to Interrupts are
provided on the main product page of the Microchip
web site for the devices listed in this data sheet. This
product page, which can be accessed using this 

contains the latest updates and additional information.

7.4.1

KEY RESOURCES

• Section 32. “Interrupts (Part III)” (DS70214)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference 

Manuals Sections

• Development Tools

In the event you are not able to access the
product page using the link above, enter
this URL in your browser: