Microchip Technology MA330028 Ficha De Dados
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533H-page 22
2011-2014 Microchip Technology Inc.
39. Module: PWM
In Complementary mode, if SWAP (IOCONx<1>)
is set from ‘0’ to ‘1’ after enabling the PWM module
(PTEN (PTCON<15>) = 1), either PWMxH or
PWMxL may stop functioning until SWAP is set
back to ‘0’.
is set from ‘0’ to ‘1’ after enabling the PWM module
(PTEN (PTCON<15>) = 1), either PWMxH or
PWMxL may stop functioning until SWAP is set
back to ‘0’.
Work around
Disable dead time.
Affected Families and Silicon Revisions
40. Module: PWM
PWM override feature is not functional.
Work around
None.
Affected Families and Silicon Revisions
41. Module: CAN
When the DMA controller is copying the received
CAN message into an appropriate message buffer
in the user-defined device RAM area, any
Read-Modify-Write operation on a CxRXFULx
(C1RXFUL1, C1RXFUL2, C2RXFUL1 and
C2RXFUL2) register may not update the
CxRXFULx register properly. The CPU can only
clear a bit in the CxRXFULx register. A
Read-Modify-Write operation successfully clears
the intended bit, but it may incorrectly clear the bit
set by the CAN module after a successful transfer
of a message into RAM by the DMA.
CAN message into an appropriate message buffer
in the user-defined device RAM area, any
Read-Modify-Write operation on a CxRXFULx
(C1RXFUL1, C1RXFUL2, C2RXFUL1 and
C2RXFUL2) register may not update the
CxRXFULx register properly. The CPU can only
clear a bit in the CxRXFULx register. A
Read-Modify-Write operation successfully clears
the intended bit, but it may incorrectly clear the bit
set by the CAN module after a successful transfer
of a message into RAM by the DMA.
Work around
Avoid Read-Modify-Write operations on C1RXFUL1,
C1RXFUL2, C2RXFUL1 and C2RXFUL2 registers.
See
C1RXFUL2, C2RXFUL1 and C2RXFUL2 registers.
See
to clear any bit in the C1RXFUL1,
C1RXFUL2, C2RXFUL1 and C2RXFUL2 registers
while developing code in C:
while developing code in C:
EXAMPLE 6:
WORK AROUND CODE
The CPU can only clear a bit in the CxRXFULx
registers, but the CPU cannot set any bit in any of
the CxRXFULx registers. Therefore, in the work
around (
registers, but the CPU cannot set any bit in any of
the CxRXFULx registers. Therefore, in the work
around (
):
• If the FNRB<5:0> (C1FIFO<5:0>) bits value is
less than or equal to 15, only one bit of the
C1RXFUL1 register will be cleared depending
on the FNRB<5:0> bits value.
C1RXFUL1 register will be cleared depending
on the FNRB<5:0> bits value.
• If the FNRB<5:0> bits value is greater than
15, only one bit of the C1RXFUL2 register will
be cleared depending on the FNRB<5:0> bits
value.
be cleared depending on the FNRB<5:0> bits
value.
This same method should be adopted for the
C2RXFUL1 and C2RXFUL2 registers.
C2RXFUL1 and C2RXFUL2 registers.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3
dsPIC33/PIC24EP128 devices
A3
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
—
dsPIC33/PIC24EP64 devices
—
dsPIC33/PIC24EP128 devices
—
dsPIC33/PIC24EP256 devices
—
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
if (C1FIFObits.FNRB <= 15)
{
C1RXFUL1 =
(0x001 C1FIFObits.FNRB);
}
else
{
C1RXFUL2 =
(0x001 (C1FIFObits.FNRB 16));
}