Microchip Technology MA330018 Ficha De Dados
© 2007-2012 Microchip Technology Inc.
DS70291G-page 451
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Motor Control PWM .......................................................... 213
Motor Control PWM Module
Motor Control PWM Module
2-Output Register Map................................................ 48
6-Output Register Map................................................ 47
6-Output Register Map................................................ 47
MPLAB ASM30 Assembler, Linker, Librarian ................... 354
MPLAB Integrated Development Environment Software .. 353
MPLAB PM3 Device Programmer .................................... 356
MPLAB REAL ICE In-Circuit Emulator System................. 355
MPLINK Object Linker/MPLIB Object Librarian ................ 354
MPLAB Integrated Development Environment Software .. 353
MPLAB PM3 Device Programmer .................................... 356
MPLAB REAL ICE In-Circuit Emulator System................. 355
MPLINK Object Linker/MPLIB Object Librarian ................ 354
N
NVM Module
O
Open-Drain Configuration ................................................. 164
Output Compare ............................................................... 209
Output Compare ............................................................... 209
P
Details ....................................................................... 430
Marking ..................................................................... 429
Marking ..................................................................... 429
Peripheral Module Disable (PMD) .................................... 156
Pinout I/O Descriptions (table) ............................................ 13
PMD Module
Pinout I/O Descriptions (table) ............................................ 13
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 85
Power-Saving Features .................................................... 155
Power-Saving Features .................................................... 155
Construction................................................................ 68
Data Access from Program Memory Using Program
Data Access from Program Memory Using Program
Data Access from, Address Generation...................... 69
Memory Map ............................................................... 35
Table Read Instructions
Memory Map ............................................................... 35
Table Read Instructions
Program Memory
Q
Quadrature Encoder Interface (QEI)................................. 227
Quadrature Encoder Interface (QEI) Module
Quadrature Encoder Interface (QEI) Module
R
CRC ............................................................................ 60
Dual Comparator......................................................... 60
Parallel Master/Slave Port .......................................... 59
Real-Time Clock and Calendar................................... 60
Dual Comparator......................................................... 60
Parallel Master/Slave Port .......................................... 59
Real-Time Clock and Calendar................................... 60
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 293
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 291
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 291
AD1CON1 (ADC1 Control 1) .................................... 286
AD1CON2 (ADC1 Control 2) .................................... 288
AD1CON3 (ADC1 Control 3) .................................... 289
AD1CON4 (ADC1 Control 4) .................................... 290
AD1CSSL (ADC1 Input Scan Select Low) ............... 295
AD1PCFGL (ADC1 Port Configuration Low) ............ 295
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 267
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 268
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 268
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 269
CiCFG1 (ECAN Baud Rate Configuration 1)............ 265
CiCFG2 (ECAN Baud Rate Configuration 2)............ 266
CiCTRL1 (ECAN Control 1)...................................... 258
CiCTRL2 (ECAN Control 2)...................................... 259
CiEC (ECAN Transmit/Receive Error Count) ........... 265
CiFCTRL (ECAN FIFO Control) ............................... 261
CiFEN1 (ECAN Acceptance Filter Enable)............... 267
CiFIFO (ECAN FIFO Status) .................................... 262
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 271,
AD1CON2 (ADC1 Control 2) .................................... 288
AD1CON3 (ADC1 Control 3) .................................... 289
AD1CON4 (ADC1 Control 4) .................................... 290
AD1CSSL (ADC1 Input Scan Select Low) ............... 295
AD1PCFGL (ADC1 Port Configuration Low) ............ 295
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 267
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 268
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 268
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 269
CiCFG1 (ECAN Baud Rate Configuration 1)............ 265
CiCFG2 (ECAN Baud Rate Configuration 2)............ 266
CiCTRL1 (ECAN Control 1)...................................... 258
CiCTRL2 (ECAN Control 2)...................................... 259
CiEC (ECAN Transmit/Receive Error Count) ........... 265
CiFCTRL (ECAN FIFO Control) ............................... 261
CiFEN1 (ECAN Acceptance Filter Enable)............... 267
CiFIFO (ECAN FIFO Status) .................................... 262
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 271,
CiINTE (ECAN Interrupt Enable) .............................. 264
CiINTF (ECAN Interrupt Flag) .................................. 263
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
CiINTF (ECAN Interrupt Flag) .................................. 263
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 274
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 274
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 274
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 275
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 275
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 277,
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 275
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 277,
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 276
CiVEC (ECAN Interrupt Code) ................................. 260
CLKDIV (Clock Divisor) ............................................ 149
CORCON (Core Control)...................................... 28, 94
DFLTCON (QEI Control) .......................................... 231
DMACS0 (DMA Controller Status 0) ........................ 138
DMACS1 (DMA Controller Status 1) ........................ 140
DMAxCNT (DMA Channel x Transfer Count)........... 137
DMAxCON (DMA Channel x Control)....................... 134
DMAxPAD (DMA Channel x Peripheral Address) .... 137
DMAxREQ (DMA Channel x IRQ Select) ................. 135
DMAxSTA (DMA Channel x RAM Start Address A) . 136
DMAxSTB (DMA Channel x RAM Start Address B) . 136
DSADR (Most Recent DMA RAM Address) ............. 141
I2CxCON (I2Cx Control)........................................... 242
I2CxMSK (I2Cx Slave Mode Address Mask)............ 246
I2CxSTAT (I2Cx Status) ........................................... 244
IFS0 (Interrupt Flag Status 0) ............................. 98, 105
IFS1 (Interrupt Flag Status 1) ........................... 100, 107
IFS2 (Interrupt Flag Status 2) ........................... 102, 109
IFS3 (Interrupt Flag Status 3) ........................... 103, 110
IFS4 (Interrupt Flag Status 4) ........................... 104, 111
INTCON1 (Interrupt Control 1) ................................... 95
INTCON2 (Interrupt Control 2) ................................... 97
INTTREG Interrupt Control and Status Register ...... 129
IPC0 (Interrupt Priority Control 0) ............................. 112
IPC1 (Interrupt Priority Control 1) ............................. 113
IPC11 (Interrupt Priority Control 11) ......................... 122
IPC14 (Interrupt Priority Control 14) ......................... 123
IPC15 (Interrupt Priority Control 15) ......................... 124
IPC16 (Interrupt Priority Control 16) ......................... 125
IPC17 (Interrupt Priority Control 17) ......................... 126
CiVEC (ECAN Interrupt Code) ................................. 260
CLKDIV (Clock Divisor) ............................................ 149
CORCON (Core Control)...................................... 28, 94
DFLTCON (QEI Control) .......................................... 231
DMACS0 (DMA Controller Status 0) ........................ 138
DMACS1 (DMA Controller Status 1) ........................ 140
DMAxCNT (DMA Channel x Transfer Count)........... 137
DMAxCON (DMA Channel x Control)....................... 134
DMAxPAD (DMA Channel x Peripheral Address) .... 137
DMAxREQ (DMA Channel x IRQ Select) ................. 135
DMAxSTA (DMA Channel x RAM Start Address A) . 136
DMAxSTB (DMA Channel x RAM Start Address B) . 136
DSADR (Most Recent DMA RAM Address) ............. 141
I2CxCON (I2Cx Control)........................................... 242
I2CxMSK (I2Cx Slave Mode Address Mask)............ 246
I2CxSTAT (I2Cx Status) ........................................... 244
IFS0 (Interrupt Flag Status 0) ............................. 98, 105
IFS1 (Interrupt Flag Status 1) ........................... 100, 107
IFS2 (Interrupt Flag Status 2) ........................... 102, 109
IFS3 (Interrupt Flag Status 3) ........................... 103, 110
IFS4 (Interrupt Flag Status 4) ........................... 104, 111
INTCON1 (Interrupt Control 1) ................................... 95
INTCON2 (Interrupt Control 2) ................................... 97
INTTREG Interrupt Control and Status Register ...... 129
IPC0 (Interrupt Priority Control 0) ............................. 112
IPC1 (Interrupt Priority Control 1) ............................. 113
IPC11 (Interrupt Priority Control 11) ......................... 122
IPC14 (Interrupt Priority Control 14) ......................... 123
IPC15 (Interrupt Priority Control 15) ......................... 124
IPC16 (Interrupt Priority Control 16) ......................... 125
IPC17 (Interrupt Priority Control 17) ......................... 126