Microchip Technology MA330031-2 Ficha De Dados
2011-2013 Microchip Technology Inc.
DS70000657H-page 235
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-7:
PWMCONx: PWMx CONTROL REGISTER
HS/HC-0
HS/HC-0
HS/HC-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTSTAT
CLSTAT
(
)
TRGSTAT
FLTIEN
CLIEN
TRGIEN
ITB
(
)
MDCS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
DTC1
DTC0
DTCP
(
)
—
MTBS
CAM
)
XPRES
(
)
IUE
)
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTSTAT:
Fault Interrupt Status bit
(
)
1
= Fault interrupt is pending
0
= No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14
CLSTAT:
Current-Limit Interrupt Status bit
1
= Current-limit interrupt is pending
0
= No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13
TRGSTAT:
Trigger Interrupt Status bit
1
= Trigger interrupt is pending
0
= No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12
FLTIEN:
Fault Interrupt Enable bit
1
= Fault interrupt is enabled
0
= Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11
CLIEN:
Current-Limit Interrupt Enable bit
1
= Current-limit interrupt is enabled
0
= Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10
TRGIEN:
Trigger Interrupt Enable bit
1
= A trigger event generates an interrupt request
0
= Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9
ITB:
Independent Time Base Mode bit
(
)
1
= PHASEx register provides time base period for this PWM generator
0
= PTPER register provides timing for this PWM generator
bit 8
MDCS:
Master Duty Cycle Register Select bit
)
1
= MDC register provides duty cycle information for this PWM generator
0
= PDCx register provides duty cycle information for this PWM generator
Note 1:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2:
These bits should not be changed after the PWMx is enabled (PTEN = 1).
3:
DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
4:
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
CAM bit is ignored.
5:
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
register must be ‘0’.