Microchip Technology MA330031-2 Ficha De Dados
2011-2013 Microchip Technology Inc.
DS70000657H-page 43
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 2
SFA:
Stack Frame Active Status bit
1
= Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and
DSWPAG values
0
= Stack frame is not active; W14 and W15 address of EDS or Base Data Space
bit 1
RND:
Rounding Mode Select bit
(
)
1
= Biased (conventional) rounding is enabled
0
= Unbiased (convergent) rounding is enabled
bit 0
IF:
Integer or Fractional Multiplier Mode Select bit
)
1
= Integer mode is enabled for DSP multiply
0
= Fractional mode is enabled for DSP multiply
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER (CONTINUED)
Note 1:
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2:
This bit is always read as ‘0’.
3:
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.