Microchip Technology MA330031-2 Ficha De Dados
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 150
2011-2013 Microchip Technology Inc.
REGISTER 8-13:
DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R-1
R-1
R-1
R-1
—
—
—
—
LSTCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
Unimplemented:
Read as ‘0’
bit 3-0
LSTCH<3:0>:
Last DMAC Channel Active Status bits
1111
= No DMA transfer has occurred since system Reset
1110
= Reserved
•
•
•
•
•
0100
= Reserved
0011
= Last data transfer was handled by Channel 3
0010
= Last data transfer was handled by Channel 2
0001
= Last data transfer was handled by Channel 1
0000
= Last data transfer was handled by Channel 0