Microchip Technology MCP1630DM-DDBS1 Ficha De Dados
©
2007 Microchip Technology Inc.
DS41211D-page 129
PIC12F683
TABLE 15-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
Operating Temperature
-40°C
≤
T
A
≤
+125°C
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
T
MC
L
MCLR Pulse Width (low)
2
5
5
—
—
—
—
—
—
μ
s
μ
s
V
DD
= 5V, -40°C to +85°C
V
DD
= 5V
31
T
WDT
Watchdog Timer Time-out
Period (No Prescaler)
Period (No Prescaler)
10
10
10
16
16
16
29
31
31
ms
ms
ms
V
DD
= 5V, -40°C to +85°C
V
DD
= 5V
32
T
OST
Oscillation Start-up Timer
Period
Period
(1, 2)
—
1024
—
T
OSC
(NOTE 3)
33*
T
PWRT
Power-up Timer Period
40
65
140
ms
34*
T
IOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
MCLR Low or Watchdog Timer
Reset
—
—
2.0
μ
s
35
V
BOR
Brown-out Reset Voltage
2.0
—
2.2
V
(NOTE 4)
36*
V
HYST
Brown-out Reset Hysteresis
—
50
—
mV
37*
T
BOR
Brown-out Reset Minimum
Detection Period
Detection Period
100
—
—
μ
s
V
DD
≤
V
BOR
*
These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
Instruction cycle period (T
CY
) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2:
By design.
3:
Period of the slower clock.
4:
To ensure these voltage tolerances, V
DD
and V
SS
must be capacitively decoupled as close to the device as
possible. 0.1
μ
F and 0.01
μ
F values in parallel are recommended.