Microchip Technology DM183021 Ficha De Dados

DS39616D-page 124

 2010 Microchip Technology Inc.

PORTE is a 4-bit wide, bidirectional port. Three pins
(RE0/AN6, RE1/AN7 and RE2/AN8) are individually
configurable as inputs or outputs. These pins have
Schmitt Trigger input buffers. When selected as an
analog input, these pins will read as ‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.    

The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE. 
The fourth pin of PORTE (MCLR/V

PP

/RE3) is an input

only pin available for PIC18F4331/4431 devices. Its
operation is controlled by the MCLRE Configuration bit

in Configuration Register 3H (CONFIG3H<7>). When
selected as a port pin (MCLRE = 0), it functions as a
digital input-only pin. As such, it does not have TRIS or
LAT bits associated with its operation. Otherwise, it
functions as the device’s master clear input. In either
configuration, RE3 also functions as the programming
voltage input during programming.

11.5.1

PORTE IN 28-PIN DEVICES

For PIC18F2331/2431 devices, PORTE is not available.
It is only available for PIC18F4331/4431 devices.

 

PORTE is only available on PIC18F4331/
4431 devices.

On a Power-on Reset, RE<2:0> are
configured as analog inputs.

On a Power-on Reset, RE3 is enabled as a
digital input only if Master Clear functionality
is disabled.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

0x3F

; Configure A/D 

MOVWF

ANSEL0

; for digital inputs

BCF

ANSEL1, 0

; 

MOVLW

0x03

; Value used to 

; initialize data 

; direction

MOVWF

TRISE

; Set RE<0> as input

; RE<1> as output

; RE<2> as input

U-0

U-0

U-0

U-0

U-0

R/W-1

R/W-1

R/W-1

—

—

—

—

—

TRISE2

TRISE1

TRISE0

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

Read as ‘0’ 

bit 2

: RE2 Direction Control bit 

1

 = Input 

0

 = Output

bit 1

: RE1 Direction Control bit 

1

 = Input 

0

 = Output

bit 0

: RE0 Direction Control bit 

1

 = Input 

0

 = Output