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 2009-2012 Microchip Technology Inc.
DS70616G-page 597
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
APPENDIX A: REVISION HISTORY
Revision A (December 2009)
This is the initial released version of this document.
Revision B (July 2010)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in Table A-1.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit Digital 
Signal Controllers and 
Microcontrollers”
Removed reference to dual triggers for Motor Control Peripherals.
Relocated the V
BUSST
 pin in all pin diagrams (see “Pin Diagrams”, Table 2 
and Table 3).
Added SCK2, SDI2, SDO2 pins in pin location 4,5 and 6 respectively in 64-pin 
QFN.
Added SCK2, SDI2, SDO2 pins in pin location 4,5 and 6 respectively in 64-pin 
TQFP.
Added SCK2, SDI2, SDO2 pins in pin location 10,11 and 12 respectively in 
100-pin TQFP.
Added SCK2, SDI2, SDO2 pins in Table 2 and Table 3.
Moved the RP30 pin to pin location 95, and the RP31 pin to pin location 96 in 
the 144-pin TQFP and 144-pin LQFP pin diagrams.
Section 1.0 “Device Overview”
Removed the SCL1 and SDA1 pins from the Pinout I/O Descriptions (see 
Table 1-1).
Section 2.0 “Guidelines for 
Getting Started with 16-bit Digital 
Signal Controllers and 
Microcontrollers”
Removed Section 2.8 “Configuration of Analog and Digital Pins During ICSP 
Operations”
Section 3.0 “CPU”
Added Note 4 to the CPU Status Register (SR) in Register 3-1.
Added the VAR bit (CORCON<15>) to Register 3-2.