Microchip Technology AC244045 Ficha De Dados
PIC16F72X/PIC16LF72X
DS41341E-page 26
© 2009 Microchip Technology Inc.
Bank 2
100h
(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
101h
TMR0
Timer0 Module Register
xxxx xxxx
102h
(2)
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
103h
(2)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
104h
(2)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
105h
—
Unimplemented
—
—
106h
—
Unimplemented
—
—
107h
—
Unimplemented
—
—
108h
CPSCON0
CPSON
—
—
—
CPSRNG1 CPSRNG0
CPSOUT
T0XCS
0--- 0000
109h
CPSCON1
—
—
—
—
CPSCH3
CPSCH2
CPSCH1
CPSCH0
---- 0000
10Ah
(1, 2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh
(2)
INTCON
GIE PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
10Ch
PMDATL
Program Memory Read Data Register Low Byte
xxxx xxxx
10Dh
PMADRL
Program Memory Read Address Register Low Byte
xxxx xxxx
10Eh
PMDATH
—
—
Program Memory Read Data Register High Byte
--xx xxxx
10Fh
PMADRH
—
—
—
Program Memory Read Address Register High Byte
---x xxxx
Bank 3
180h
(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h
(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
183h
(2)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
184h
(2)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
185h
ANSELA
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
186h
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
187h
—
Unimplemented
—
—
188h
ANSELD
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111
189h
(3)
ANSELE
—
—
—
—
—
ANSE2
ANSE1
ANSE0
---- -111
18Ah
(1, 2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh
(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
18Ch
PMCON1
Reserved
—
—
—
—
—
—
RD
1--- ---0
18Dh
—
Unimplemented
—
—
18Eh
—
Unimplemented
—
—
18Fh
—
Unimplemented
—
—
TABLE 2-1:
PIC16F72X/PIC16LF72X SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
transferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
4:
Accessible only when SSPM<3:0> = 1001.
5:
Accessible only when SSPM<3:0>
≠ 1001.
6:
This bit is always ‘1’ as RE3 is input only.