Microchip Technology MA330016 Ficha De Dados
© 2007-2011 Microchip Technology Inc.
DS70290J-page 163
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
16.2
I
2
C Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
, contains the latest updates
and additional information.
16.2.1
KEY RESOURCES
• Section 13. “Inter-Integrated Circuit™ (I
2
C™)”
(DS70195)
16.3
I
2
C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting
data.
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read.
bytes are read.
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation.
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-bit Address
• A status bit, ADD10, indicates 10-bit Address
mode.
• I2CxBRG acts as the Baud Rate Generator
(BRG) reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
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