Microchip Technology TMPSNS-RTD1 Ficha De Dados
© 2009 Microchip Technology Inc.
DS39632E-page 235
PIC18F2455/2550/4455/4550
19.4.12
ACKNOWLEDGE SEQUENCE
TIMING
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
BRG
)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
BRG
. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into an inactive state
(Figure 19-25).
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into an inactive state
(Figure 19-25).
19.4.12.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
19.4.13
STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Enable bit, PEN
(SSPCON2<2>). At the end of a receive/transmit, the
SCL line is held low after the falling edge of the ninth
clock. When the PEN bit is set, the master will assert
the SDA line low. When the SDA line is sampled low,
the Baud Rate Generator is reloaded and counts down
to 0. When the Baud Rate Generator times out, the
SCL pin will be brought high and one T
receive/transmit by setting the Stop Enable bit, PEN
(SSPCON2<2>). At the end of a receive/transmit, the
SCL line is held low after the falling edge of the ninth
clock. When the PEN bit is set, the master will assert
the SDA line low. When the SDA line is sampled low,
the Baud Rate Generator is reloaded and counts down
to 0. When the Baud Rate Generator times out, the
SCL pin will be brought high and one T
BRG
(Baud Rate
Generator rollover count) later, the SDA pin will be
deasserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A T
deasserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A T
BRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 19-26).
(Figure 19-26).
19.4.13.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 19-25:
ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 19-26:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: T
BRG
= one Baud Rate Generator period.
SDA
SCL
Set SSPIF at the
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
Cleared in
T
BRG
T
BRG
end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software
Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for T
BRG
, followed by SDA = 1 for T
BRG
ninth clock
SCL brought high after T
BRG
Note: T
BRG
= one Baud Rate Generator period.
T
BRG
T
BRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
T
BRG
to setup Stop condition
ACK
P
T
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set