Freescale Semiconductor FRDM-FXS-9AXIS Ficha De Dados

Sensors
Freescale Semiconductor, Inc.

97

2

05/2013

• Changed title of document.
• Table 1: Added footnotes.
• Table 2: Added footnotes. Updated Sensitivity change with temperature row Typ value from 0.008 to 0.01. 

Changed Zero-g level change versus temperature Typ value from ±0.15 to ±0.2. Changed Typ value in 
Hysteresis from ±1 to ±0.5. Updated Nonlinearity row from TBD to 0.25 %FS

ACCEL

. Self-Test output change row: 

updated Typ values from 143, 255, and 1330 to 249, 335, and 1640 respectively and changed Symbol column 
for all axes. Deleted ODR accuracy row. Moved Output data bandwidth row to Table 4. Typ values, added min 
values. Removed footnote 2 from table.

• Table 3: Updated Symbol names for all rows. Updated Unit column for Hysteresis and added note 3 to 

Nonlinearity and Magnetometer output noise rows. Removed Temperature sensor repeatability row and 
footnote 4. Updated all Typ values for Magnetometer output noise row(s). Changed Self-test output change row 
Symbol from Vst to STOC

mag

, updated Typ values from 1164, 1130, 41 to 1161, -1130 and -43 respectively. 

Removed Typ and Max values and updated min values. Removed Min and Max values from Output data 
bandwidth row, added Min value. Footnote 2: changed applied magnetic field values from -1200 

μ

T to -1000

μ

T 

to -1200 

μ

T to 1000 

μ

T

• Table 4: Added Symbol for Maximum output data rate in hybrid mode. 
• Table 5: Updated Symbol names for most rows. Updated Test conditions column for Hybrid mode and Magnetic 

mode rows. Updated Standby mode current over-temperature range row Max value column from 16 to 10. 
Moved Typ value for Digital high-level input voltage RST pin to Min column, and moved Typ value for Digital low-
level input voltage RST pin to Max column. Removed BW rows (two) from table. Changed Power-on ramp time 
to VDD rise time. Corrected footnote order.

• Added paragraph for Section 4.5.
• Table 9: Removed note regarding preproduction parts and addresses. 
• Section 5.2.1: Updated first paragraph with point-to-point information.
• Added text in paragraph for Section 5.2.3.
• Table 14: Updated PL_CFG register Default Hex Value from 0x83 to 0x80, PL_BF_ZCOMP from 0x00 to 0x84, 

PL_THS_REG from 0x1A to 0x44 Changed Reserved bit address from 0x7D-0xFF to 0x79-0xFF. Added Auto-
incremented Address information for register addresses 0x32-0x78.

• Updated NOTE following Table 14. 
• Corrected bit names in Table 17. 
• Table 25: Updated last two rows, ODR accelerometer or magnetometer only modes was 6.3 to 6.25, and 1.6 to 

1.5625 respectively; ODR hybrid mode was 3.15 to 3.125 and 0.8 to 0.7813 respectively.

• Table 34: updated rst Description.
• Added Table 36.
• Added text in paragraph for Section 9.3.1.
• Corrected bit names in Table 63.
• Table 65: Changed bits 0 and 1 values from 1 to 0.
• Table 69: Change bits 0 and 1 values from 03010 to 00b100 and changed bits 7 and 6 values from 0 to 0b10.
• Table 70: Updated Descriptions for zlock, default value from 00 

→ 

13° to 0x04 

→ ∼

28° and maximum value from 

07 

→ 

44° to 0x07 

→

 ~44°. Updated Descriptions for bkfr, default value from 10 

→ 

±75° to 0b10 

→ 

±70°.

• Table 73: Updated bits 0 and 1 value from 0b010 to 0b100 and bits 2-7 value from 0b0_0011 to 0b0_1000.
• New Section 11 Package Thermal Characteristics. 
• Updated package outline.
• Added Appendix, errata information.