Freescale Semiconductor Tower System Kit TWR-56F8400 TWR-56F8400-KIT TWR-56F8400-KIT Guia De Informação

• Selectable supply reference source
• Powerdown mode to conserve power when not in use
• Output routed to internal comparator input
• Less than 20 µA power consumption

• Full rail-to-rail comparison range
• Support for high speed mode and low speed mode
• Selectable input source includes external pins and internal DACs
• Programmable output polarity
• 6-bit programmable DAC as voltage reference per comparator
• Three programmable hysteresis levels
• Selectable interrupt on rising edge, falling edge, or toggle of comparator output

• Maximum 25 Mbps baud rate
• Selectable baud rate clock sources for low baud rate communication
• Baud rate as low as Baudrate_Freq_in / 8192
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four-word-deep FIFOs available on transmit and receive buffers
• Programmable length transmissions (2 bits to 16 bits)
• Programmable transmit and receive shift order (MSB as first bit transmitted)

• Operating clock up to two times CPU operating frequency
• Four-word-deep FIFOs available on both transmit and receive buffers
• Standard mark/space non-return-to-zero (NRZ) format
• 13-bit integer and 3-bit fractional baud rate selection
• Full-duplex or single-wire operation
• Programmable 8-bit or 9-bit data format
• Error detection capability
• Two receiver wakeup methods:

• Idle line
• Address mark

• 1/16 bit-time noise detection

• Compatible with I2C bus standard
• Support for System Management Bus (SMBus) specification, version2
• Multi-master operation
• General call recognition
• 10-bit address extension
• Dual slave addresses
• Programmable glitch input filter

Freescale Semiconductor, Inc.

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