Freescale Semiconductor Tower System Kit TWR-56F8400 TWR-56F8400-KIT TWR-56F8400-KIT Guia De Informação

• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual Harvard architecture

• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data bus, and one 16-bit instruction bus
• 32-bit data accesses
• Support for concurrent instruction fetches in the same cycle and dual data accesses in the same cycle
• 20 addressing modes

• As many as 100 million instructions per second (MIPS) at 100 MHz core frequency
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical

operation

• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator (MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Four 36-bit accumulators, including extension bits
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, effectively supporting DSP and Fast Fourier Transform algorithms

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Freescale Semiconductor, Inc.