Freescale Semiconductor Evaluation Board for MPC5566MZP132 MPC5566EVB MPC5566EVB Ficha De Dados

Freescale Semiconductor

10

Power sequencing between the 1.5 V power supply and V

DDSYN

 or the RESET power supplies is required 

if using an external 1.5 V power supply with V

RC33

 tied to ground (GND). To avoid power-sequencing, 

V

RC33

 must be powered up within the specified operating range, even if the on-chip voltage regulator 

controller is not used. Refer to 

”

 and 

.

”

Power sequencing requires that V

DD33

 must reach a certain voltage where the values are read as ones 

before the POR signal negates. Refer to 

.

”

Although power sequencing is not required between V

RC33

 and V

DDSYN

 during power up, V

RC33

 must 

not lead V

DDSYN

 by more than 600 mV or lag by more than 100 mV for the V

RC

 stage turn-on to operate 

within specification. Higher spikes in the emitter current of the pass transistor occur if V

RC33

 leads or lags 

V

DDSYN

 by more than these amounts. The value of that higher spike in current depends on the board power 

supply circuitry and the amount of board level capacitance.

Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase 
of the current consumed by V

RC33

. If V

RC33

 lags V

DDSYN

 by more than 100 mV, the increase in current 

consumed can drop V

DD

 low enough to assert the 1.5 V POR again. Oscillations are possible when the 

9

Absolute value of slew rate on power supply pins

—

—

50

V/ms

10

Required gain at Tj: 
I

DD

 



 I

VRCCTL

 (@ f

sys

 = f

MAX

) 

, 

, 8, 9

– 40

o

 C

BETA 

10

60

—

—

25

o

 C

65

—

—

150

o

 C 

85

500

—

1

The internal POR signals are V

POR15

, V

POR33

, and V

POR5

. On power up, assert RESET before the internal POR negates. 

RESET must remain asserted until the power supplies are within the operating conditions as specified in 

 DC Electrical 

Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the 
internal POR asserts.

2

V

IL_S

 (

, Spec15) is guaranteed to scale with V

DDEH6

 down to V

POR5

.

3

Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.

4

It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.

5

At peak current for device.

6

Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal 
traces/routing from the V

RCCTL

 package signal to the base of the external pass transistor and between the emitter of the pass 

transistor to the V

DD

 package signals must have a maximum of 100 nH inductance and minimal resistance 

(less than 1 

). V

RCCTL

 must have a nominal 1 

F phase compensation capacitor to ground. V

DD

 must have a 20 

F (nominal) 

bulk capacitor (greater than 4 

F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of 

eight 0.01 

F, two 0.1 F, and one 1 F capacitors around the package on the V

DD

 supply signals.

7

I

VRCCTL

 is measured at the following conditions: V

DD 

= 1.35 V, V

RC33 

= 3.1 V, V

VRCCTL

 = 2.2 V.

8

Refer to 

 for the maximum operating frequency.

9

Values are based on I

DD

 from high-use applications as explained in the I

DD

 Electrical Specification. 

10

BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I

DD

 



 I

VRCCTL

).