Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Ficha De Dados
Códigos do produto
KIT912F634EVME
Functional Description and Application Information
Serial Communication Interface (S08SCIV4)
MM912F634
Freescale Semiconductor
113
4.15.2.2
SCI Control Register 1 (SCIC1)
This read/write register is used to control various optional features of the SCI system.
Table 128. SCI Control Register 1 (SCIC1)
Offset
0x42
Access: User read/write
7
6
5
4
3
2
1
0
R
LOOPS
0
RSRC
M
0
ILT
PE
PT
W
Reset
0
0
0
0
0
0
0
0
Note:
101. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 129. SCIC1 Field Descriptions
Field
Description
7
LOOPS
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the
transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD
transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD
pin is not used by SCI.
5
RSRC
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver
input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter
output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter
output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
4
M
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
2
ILT
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count
toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of
the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s
in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including
the parity bit, is even.
0 Even parity.
1 Odd parity.
in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including
the parity bit, is even.
0 Even parity.
1 Odd parity.