Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Ficha De Dados
Códigos do produto
KIT912F634EVME
Functional Description and Application Information
General Purpose I/O - PTB[0…2]
MM912F634
Freescale Semiconductor
125
4.17.4
Register definition
4.17.4.1
Port B Configuration Register 1 (PTBC1)
NOTE
The pull-up resistor is not active once the port is configured as an output.
4.17.4.2
Port B Configuration Register 2 (PTBC2)
Table 145. Port B Configuration Register 1 (PTBC1)
Offset
0x20
Access: User read/write
7
6
5
4
3
2
1
0
R
0
PUEB2
PUEB1
PUEB0
0
DDRB2
DDRB1
DDRB0
W
Reset
0
0
0
0
0
0
0
0
Note:
111. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 146. PTBC1 - Register Field Descriptions
Field
Description
6-4
PUEB[2-0]
Pull-up Enable Port B[2…0]
0 - Pull-up disabled on PTBx pin.
1- Pull-up enabled on PTBx pin.
0 - Pull-up disabled on PTBx pin.
1- Pull-up enabled on PTBx pin.
2-0
DDRB[2-0]
Data Direction Port B[2….0]
0 - PTBx configured as input.
1 - PTBx configured as output.
0 - PTBx configured as input.
1 - PTBx configured as output.
Table 147. Port B Configuration Register 2 (PTBC2)
Offset
0x21
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
PWMCS
PWMEN
SERMOD
W
Reset
0
0
0
0
0
0
0
0
Note:
112. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 148. PTBC2 - Register Field Descriptions
Field
Description
3
PWMCS
PWM Channel Select PTB2. See
0 - PWM Channel 0 selected as PWM Channel for PTB2
1 - PWM Channel 1 selected as PWM Channel for PTB2
1 - PWM Channel 1 selected as PWM Channel for PTB2
2
PWMEN
PWM Enable for PTB2. See
.
0 - PWM disabled on PTB2
1 - PWM enabled on PTB2 (Channel as selected with PWMCS)
1 - PWM enabled on PTB2 (Channel as selected with PWMCS)
1-0
SERMOD
for details.
00 - Mode 0, SCI internally connected the LIN Physical Layer Interface. PTB0 and PTB1 are Digital I/Os
01 - Mode 1, SCI connected to PTB0 and PTB1 (external SCI mode)
10 - Mode 2, LIN Physical Layer Interface connected to PTB0 and PTB1 (external LIN mode)
11 - Mode 3, SCI internally connected the LIN Physical Layer Interface and PTB0 and PTB1 are connected both as outputs
01 - Mode 1, SCI connected to PTB0 and PTB1 (external SCI mode)
10 - Mode 2, LIN Physical Layer Interface connected to PTB0 and PTB1 (external LIN mode)
11 - Mode 3, SCI internally connected the LIN Physical Layer Interface and PTB0 and PTB1 are connected both as outputs
(Observe mode)