Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Ficha De Dados
Códigos do produto
KIT912F634EVME
Functional Description and Application Information
Computer Operating Properly (S12SCOPV1)
MM912F634
Freescale Semiconductor
263
4.35
Computer Operating Properly (S12SCOPV1)
4.35.1
Introduction
This section describes the functionality of the Computer Operating Properly module (COP), a sub-block of the HCS12S core
platform.The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly.
If the COP times out a system reset is initiated. Two types of COP operation are available: Window COP or Normal COP
platform.The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly.
If the COP times out a system reset is initiated. Two types of COP operation are available: Window COP or Normal COP
When COP is enabled, sequential writes of $55 and $AA (in this order) are expected to the ARMCOP register during the selected
timeout period. Once this is done, the COP timeout period restarts. If the program fails to do this the S12SCRG will initiate a reset.
timeout period. Once this is done, the COP timeout period restarts. If the program fails to do this the S12SCRG will initiate a reset.
4.35.1.1
Overview
A block diagram of the COP is shown in
Figure 82. Block Diagram
4.35.1.2
Features
The COP includes these distinctive features:
•
Watchdog timer with a timeout clear window.
•
Default maximum COP rate and no Window COP in Special Single Chip mode after system reset.
•
Auto COP rate load after system reset in SoC Normal mode. (For source of COP rate bits please refer to the Device
User Guide)
User Guide)
•
Software selectable COP operation in WAIT and STOP mode.
•
Customer selectable COP off while BDM active (debugging session).
Modulus Down Counter
ARMCOP-Register
Int_Ref_Clock
CR[2:0]
Control Logic
COP reset
request
WCOP
SSC_Mode
(2
6
,..., 2
16
)