Freescale Semiconductor KIT912F634EVME Evaluation Kit KIT912F634EVME KIT912F634EVME Ficha De Dados
Códigos do produto
KIT912F634EVME
Functional Description and Application Information
Serial Peripheral Interface (S12SPIV4)
MM912F634
Freescale Semiconductor
330
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift
register is driven out on the pin. The same pin is also the serial input to the shift register.
register is driven out on the pin. The same pin is also the serial input to the shift register.
•
The SCK is output for the master mode and input for the slave mode.
•
The SS is the input or output for the master mode, and it is always the input for the slave mode.
•
The bidirectional mode does not affect SCK and SS functions.
4.38.4.6
Error Conditions
The SPI has one error condition:
•
Mode fault error
4.38.4.6.1
Mode Fault Error
NOTE
If a mode fault error occurs and a received data byte is pending in the receive shift register,
this data byte will be lost.
this data byte will be lost.
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may
be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation. The MODF bit in
the SPI status register is set automatically, provided the MODFEN bit is set.
be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation. The MODF bit in
the SPI status register is set automatically, provided the MODFEN bit is set.
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this case,
the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin
is a dedicated input pin. Mode fault error doesn’t occur in slave mode.
the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin
is a dedicated input pin. Mode fault error doesn’t occur in slave mode.
If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So
SCK, MISO, and MOSI pins are forced to be high-impedance inputs, to avoid any possibility of conflict with another output driver.
A transmission in progress is aborted and the SPI is forced into idle state.
SCK, MISO, and MOSI pins are forced to be high-impedance inputs, to avoid any possibility of conflict with another output driver.
A transmission in progress is aborted and the SPI is forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI
(MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system
configured in slave mode.
(MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system
configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set), followed by a write to the SPI
control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
Table 415. Normal Mode and Bidirectional Mode
When SPE = 1
Master Mode MSTR = 1
Slave Mode MSTR = 0
Normal Mode
SPC0 = 0
Bidirectional Mode
SPC0 = 1
SPI
MOSI
MISO
Serial Out
Serial In
SPI
MOSI
MISO
Serial In
Serial Out
SPI
MOMI
Serial Out
Serial In
BIDIROE
SPI
SISO
Serial In
Serial Out
BIDIROE