Freescale Semiconductor Tower System Kit for MC9S08PT60 Series TWR-S08PT60-KIT TWR-S08PT60-KIT Ficha De Dados

4. Load capacitors (C

1

,C

2

), feedback resistor (R

F

) and series resistor (R

S

) are incorporated internally when RANGE = HGO =

0.

5. This parameter is characterized and not tested on each device.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed,

DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

Bus

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V

DD

 and V

SS

 and variation in crystal oscillator frequency increase the C

Jitter

 percentage

for a given interval.

EXTAL

XTAL

Crystal or Resonator

R

S

C

2

R

F

C

1

This section provides details about program/erase times and program-erase endurance for
the flash and EEPROM memories.

D

Supply voltage for program/erase -40

°C to 105 °C

V

prog/erase

2.7

—

5.5

V

D

Supply voltage for read operation

V

Read

2.7

—

5.5

V

D

NVM Bus frequency

f

NVMBUS

1

—

25

MHz

D

NVM Operating frequency

f

NVMOP

0.8

—

1.05

MHz

D

Erase Verify All Blocks

t

VFYALL

—

—

17030

t

cyc

D

Erase Verify Flash Block

t

RD1BLK

—

—

16977

t

cyc

D

Erase Verify EEPROM Block

t

RD1BLK

—

—

843

t

cyc

D

Erase Verify Flash Section

t

RD1SEC

—

—

517

t

cyc

D

Erase Verify EEPROM Section

t

DRD1SEC

0.10

0.10

0.11

ms

20

Freescale Semiconductor, Inc.