Freescale Semiconductor Starter Kit for MC9S12G TRK-USB-S12G128 TRK-USB-S12G128 Ficha De Dados
Códigos do produto
TRK-USB-S12G128
Serial Communication Interface (S12SCIV5)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
691
20.4.6
Receiver
Figure 20-20. SCI Receiver Block Diagram
20.4.6.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
20.4.6.2
Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
All 1s
M
WAKE
ILT
PE
PT
RE
H
8
7
6
5
4
3
2
1
0
L
11-Bit Receive Shift Register
Stop
Star
t
Data
Wakeup
Parity
Checking
MSB
SCI Data Register
R8
ILIE
RWU
RDRF
OR
NF
FE
PE
Internal Bus
Bus
SBR12:SBR0
Baud Divider
Clock
IDLE
RAF
Recovery
Logic
RXPOL
LOOPS
Loop
RSRC
Control
SCRXD
From TXD Pin
or Transmitter
or Transmitter
Idle IRQ
RDRF/OR
IRQ
IRQ
Break
Detect Logic
Active Edge
Detect Logic
BRKDFE
BRKDIE
BRKDIF
RXEDGIE
RXEDGIF
Break IRQ
RX Active Edge IRQ
RIE