Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51EXP MCIMX51EXP Ficha De Dados

Códigos do produto

MCIMX51EXP

Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6

Freescale Semiconductor

131

4.7.13

SCAN JTAG Controller (SJC) Timing Parameters

Figure 88

depicts the SJC test clock input timing.

depicts the SJC boundary scan timing.

depicts the TRST timing with respect to TCK.

depicts the SJC test access port. Signal

parameters are listed in

Figure 88. Test Clock Input Timing Diagram

Figure 89. Boundary Scan (JTAG) Timing Diagram

TCK

(Input)

VIH

VIL

SJ1

SJ2

SJ3

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Data

Outputs

VIH

VIL

Input Data Valid

Output Data Valid

SJ4

SJ5

SJ6

SJ7

SJ6