Freescale Semiconductor MC9S12G128 Evaluation Board TWR-S12G128-KIT TWR-S12G128-KIT Ficha De Dados
Códigos do produto
TWR-S12G128-KIT
Analog-to-Digital Converter (ADC10B16CV2)
MC9S12G Family Reference Manual,
Rev.1.23
534
Freescale Semiconductor
15.3.2.5
ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
0
1
Reserved
1
0
Finish current conversion, then freeze
1
1
Freeze Immediately
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
SMP2
SMP1
SMP0
PRS[4:0]
W
Reset
0
0
0
0
0
1
0
1
Figure 15-7. ATD Control Register 4 (ATDCTL4)
Table 15-12. ATDCTL4 Field Descriptions
Field
Description
7–5
SMP[2:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
lists the available sample time lengths.
4–0
PRS[4:0]
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
is calculated as follows:
Refer to Device Specification for allowed frequency range of f
ATDCLK
.
Table 15-13. Sample Time Select
SMP2
SMP1
SMP0
Sample Time
in Number of
in Number of
ATD Clock Cycles
0
0
0
4
0
0
1
6
0
1
0
8
0
1
1
10
1
0
0
12
1
0
1
16
1
1
0
20
1
1
1
24
Table 15-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1
FRZ0
Behavior in Freeze Mode
f
ATDCLK
f
BUS
2
PRS
1
+
(
)
×
-------------------------------------
=