Freescale Semiconductor MC9S12G128 Evaluation Board TWR-S12G128-KIT TWR-S12G128-KIT Ficha De Dados
Códigos do produto
TWR-S12G128-KIT
16 KByte Flash Module (S12FTMRG16K1V1)
MC9S12G Family Reference Manual,
Rev.1.23
788
Freescale Semiconductor
24.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
executing (CCIF=0).
0x0011
FRSV5
R
0
0
0
0
0
0
0
0
W
0x0012
FRSV6
R
0
0
0
0
0
0
0
0
W
0x0013
FRSV7
R
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R
FDIVLD
FDIVLCK
FDIV[5:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-5. Flash Clock Divider Register (FCLKDIV)
Table 24-7. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Address
& Name
7
6
5
4
3
2
1
0
Figure 24-4. FTMRG16K1 Register Summary (continued)