Freescale Semiconductor TWR-S12G64 Scalable Platform for Automotive Applications TWR-S12G64-KIT TWR-S12G64-KIT Ficha De Dados
Códigos do produto
TWR-S12G64-KIT
240 KByte Flash Module (S12FTMRG240K2V1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
1159
31.3.2.9.1
P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed.
specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
31.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
Table 31-21. P-Flash Protection Scenario Transitions
From
Protection
Scenario
To Protection Scenario
1
1
Allowed transitions marked with X, see
for a definition of the scenarios.
0
1
2
3
4
5
6
7
0
X
X
X
X
1
X
X
2
X
X
3
X
4
X
X
5
X
X
X
X
6
X
X
X
X
7
X
X
X
X
X
X
X
X
Offset Module Base + 0x0009
7
6
5
4
3
2
1
0
R
DPOPEN
DPS[6:0]
W
Reset
F
1
1
Loaded from IFR Flash configuration field, during reset sequence.
F
F
F
F
Figure 31-15. EEPROM Protection Register (EEPROT)