Freescale Semiconductor TWR-S12G64 Scalable Platform for Automotive Applications TWR-S12G64-KIT TWR-S12G64-KIT Ficha De Dados
Códigos do produto
TWR-S12G64-KIT
Analog-to-Digital Converter (ADC12B8CV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
447
12.2
Signal Description
This section lists all inputs to the ADC12B8C block.
12.2.1
Detailed Signal Descriptions
12.2.1.1
ANx (x = 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel
x. It can also be configured as digital port or external trigger
for the ATD conversion.
12.2.1.2
ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connectivity of these inputs!
12.2.1.3
VRH, VRL
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
12.2.1.4
VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC12B8C block.
12.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B8C.
12.3.1
Module Memory Map
gives an overview on all ADC12B8C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
ATDCTL0
R
Reserved
0
0
0
WRAP3
WRAP2
WRAP1
WRAP0
W
0x0001
ATDCTL1
R
ETRIGSEL
SRES1
SRES0
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0002
ATDCTL2
R
0
AFFC
Reserved ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
W
= Unimplemented or Reserved
Figure 12-2. ADC12B8C Register Summary (Sheet 1 of 2)