Freescale Semiconductor TWR-S12G64 Scalable Platform for Automotive Applications TWR-S12G64-KIT TWR-S12G64-KIT Ficha De Dados
Códigos do produto
TWR-S12G64-KIT
16 KByte Flash Module (S12FTMRG16K1V1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
789
24.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
6
FDIVLCK
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV field in normal mode.
5–0
FDIV[5:0]
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
during Flash program and erase algorithms.
shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to
,
”
for more information.
Table 24-8. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
FDIV[5:0]
BUSCLK Frequency
(MHz)
FDIV[5:0]
MIN
1
1
BUSCLK is Greater Than this value.
MAX
2
2
BUSCLK is Less Than or Equal to this value.
MIN
1.0
1.6
0x00
16.6
17.6
0x10
1.6
2.6
0x01
17.6
18.6
0x11
2.6
3.6
0x02
18.6
19.6
0x12
3.6
4.6
0x03
19.6
20.6
0x13
4.6
5.6
0x04
20.6
21.6
0x14
5.6
6.6
0x05
21.6
22.6
0x15
6.6
7.6
0x06
22.6
23.6
0x16
7.6
8.6
0x07
23.6
24.6
0x17
8.6
9.6
0x08
24.6
25.6
0x18
9.6
10.6
0x09
10.6
11.6
0x0A
11.6
12.6
0x0B
12.6
13.6
0x0C
13.6
14.6
0x0D
14.6
15.6
0x0E
15.6
16.6
0x0F
Table 24-7. FCLKDIV Field Descriptions (continued)
Field
Description