AMD Phenom 8450 Triple-Core HD8450WCGHBOX Manual Do Utilizador

AMD

Códigos do produto

HD8450WCGHBOX

Product Errata

15

Revision Guide for AMD Family 10h Processors

41322

Rev. 3.16

February 2008

Incorrect Memory Controller Operation In Ganged Mode

X

HyperTransport™ Link RTT and RON Specification
Violations

X

Time Stamp Counter May Yield An Incorrect Value

X

X

Memory Instability After PWROK Assertion

X

X

DRAM Phy Configuration Access Failures

X

Single Machine Check Error May Report Overflow

No fix planned.

L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit

X

X

Hardware Memory Clear Is Not Supported After Software
DRAM Initialization

X

X

Performance Counters Do Not Accurately Count MFENCE
or SFENCE Instructions

X

X

MWAIT Power Savings May Not Be Realized when Two or
More Cores Monitor the Same Address

X

X

Processor Stall in C1 Low Power State

X

X

Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response

X

X

CVTSD2SS and CVTPD2PS Instructions May Not Round
to Zero

No fix planned.

FST and FSTP Instructions May Calculate Operand
Address in Incorrect Mode

X

X

Inaccurate Temperature Measurement

X

X

Table 9.

Cross-Reference of Product Revision to Errata (Continued)

No.

Errata Description

Revision

Number

DR-BA

DR-B2