Analog Devices ADP1660 Evaluation Board ADP1660CB-EVALZ ADP1660CB-EVALZ Ficha De Dados
Códigos do produto
ADP1660CB-EVALZ
Data Sheet
ADP1660
Rev. 0 | Page 25 of 28
PCB LAYOUT
Poor layout can affect performance, causing electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
problems, ground bounce, and power losses. Poor layout can also
affect regulation and stability. Figure 32 shows an optimized
layout implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
interference (EMI) and electromagnetic compatibility (EMC)
problems, ground bounce, and power losses. Poor layout can also
affect regulation and stability. Figure 32 shows an optimized
layout implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and large currents.
high switching frequencies and large currents.
• Use as wide a trace as possible between the inductor and
the SW pin. The easiest path for this trace is through the
center of the output capacitor.
center of the output capacitor.
• Route the LED1/LED2 path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
of the board to help with thermal dissipation.
• Use a ground plane with two or three vias connecting to
the component side ground near the output capacitor to
reduce noise interference on sensitive circuit nodes.
reduce noise interference on sensitive circuit nodes.
Analog Devices applications engineers can be contacted
through the Analog Devices sales team to discuss different
through the Analog Devices sales team to discuss different
layouts based on system design constraints.
LED2
DIGITAL
INPUT/
OUTPUT
INPUT/
OUTPUT
PGND
C1
L1
LED1
AREA = 16.4mm
2
1
1018-
027
Li-ION+
INDUCTOR
C2
Figure 32. Layout of the
Driving a High Power White LED