Analog Devices ADP1660 Evaluation Board ADP1660CB-EVALZ ADP1660CB-EVALZ Ficha De Dados
Códigos do produto
ADP1660CB-EVALZ
Data Sheet
ADP1660
Rev. 0 | Page 5 of 28
I
2
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter
Min
Max
Unit
Description
f
SCL
1000
kHz
SCL clock frequency
t
HIGH
0.26
μs
SCL high time
t
LOW
0.5
μs
SCL low time
t
SU, DAT
50
ns
Data setup time
t
HD, DAT
0
0.9
μs
Data hold time
t
SU, STA
0.26
μs
Setup time for repeated start
t
HD, STA
0.26
μs
Hold time for start/repeated start
t
BUF
0.5
μs
Bus free time between a stop and a start condition
t
SU, STO
0.26
μs
Setup time for stop condition
t
R
120
ns
Rise time of SCL and SDA
t
F
120
ns
Fall time of SCL and SDA
t
0
50
ns
Pulse width of suppressed spike
400
pF
Capacitive load for each bus line
1
Guaranteed by design.
2
C
B
is the total capacitance of one bus line in picofarads.
Timing Diagram
SDA
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Sr
P
S
t
LOW
t
R
t
HD, DAT
t
HIGH
t
SU, DAT
t
F
t
F
t
SU, STA
t
HD, STA
t
SP
t
SU, STO
t
BUF
t
R
1
1
01
8-
00
3
Figure 3. I
2
C-Compatible Interface Timing Diagram