Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados
Códigos do produto
AT91SAM9N12-EK
Preface
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
xix
Key to timing diagram conventions
Signal naming
The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW
signals:
active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW
signals:
Prefix H
Denotes Advanced High-performance Bus (AHB) signals.
Prefix n
Denotes active-LOW signals except in the case of AHB or Advanced
Peripheral Bus APB reset signals. These are named HRESETn and
PRESETn respectively.
Peripheral Bus APB reset signals. These are named HRESETn and
PRESETn respectively.
Prefix DH
Denotes data side AHB signals.
Prefix IH
Denotes instruction side AHB signals.
Prefix DR
Denotes data side TCM interface signals.
Prefix IR
Denotes instruction side TCM interface signals.
Prefix ETM Denotes ETM interface signals.
Prefix DBG Denotes debug/JTAG signals.
Prefix CP
Denotes coprocessor interface signals.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus